PCI stands for xe2x80x9cperipheral component interfacexe2x80x9d defined by the PCI Special Interest Group in an effort to stem development of various local bus architectures. PCI bus communications include transactions between xe2x80x9cmasterxe2x80x9d and xe2x80x9cslavexe2x80x9d devices connected to the bus. The prior art is familiar with PCI bus architectures and master-slave communication protocols.
To enhance PCI bus performance, a xe2x80x9cdelayed transactionxe2x80x9d is implemented when a master initiates a transaction to a slave that cannot immediately respond. Delayed transactions are used to improve bus performance. Specifically, in a delayed transaction, a slave captures the transaction request informationxe2x80x94e.g., address, command, byte enable and dataxe2x80x94and prompts the master to retry the cycle at a later time. The slave then proceeds to execute the transaction and stores the resulting information. When the master attempts the cycle again, the slave has the data that is needed and completes the transaction.
By way of example, the prior art is familiar with PCI bridge chips that connect together two PCI buses. These bridge chips can be used, for example, in transferring data from an initiating PCI bus to a target PCI bus. One prior art bridge chip is the DEC21154 chip from Intel, for example. These prior art bridge chips generally provide for sequential transfer of large bursts of data across the bridge. In the case of a delayed transaction from a PCI to a PCI bridge, the slave executes the delayed transaction on the target or secondary bus.
A problem occurs in prior art PCI delayed transaction architecture when an initiating master does not retry a cycle that was previously categorized as a delayed transaction. Without a way to clear the cycle information captured by the slave, a deadlock can occur: the slave waits for the initiating master to return and refuses to accept new cycles. This problem is detailed in FIG. 1, illustrating a master 10 attempting communication from a primary PCI bus P1 to a secondary PCI bus P2, and ultimately to SCSI device 12. The bridge chip 14 serves as a slave for the transactions issued by the master 10. In early PCI bus protocol, if the master 10 initiates a read on PCI bus P1 and the target PCI bus P2 cannot respond, the PCI bus P1 could actually lock until the target bus P2 responds. With delayed transaction PCI architecture, if the target device bus P2 cannot respond to the master-initiated read, a retry is issued in a delayed transaction at the bridge chip 14 and the primary bus P1 remains free for other transactions. However, the bridge chip 14 has a finite number of delayed transaction buffers, shown in FIG. 2.
FIG. 2 shows prior art slave delayed transaction buffers 16 such as used in the bridge chip 14 of FIG. 1. FIG. 2 also illustrates representative data 18 (e.g., the transaction request information) associated with the buffers 16. In the event that the master 10 does not retry the transaction associated with the data 18, then other buffers 16 are used for storagexe2x80x94until all buffers 16 are used and full, thereafter locking delayed transaction data 18 within the buffer 16. In such a situation, the target devicexe2x80x94i.e., the bridge chip 14 in this examplexe2x80x94waits for the initiating master to return and refuses to accept new cycles, locking out transactions between the master and, for example, the SCSI device 12.
One object of the invention thus provides delayed transaction architecture which solves the aforementioned problem. Another object of the invention is to provide a PCI bridge chip that controls delayed transaction buffers to prevent delayed transaction lockout as described in FIGS. 1 and 2. Yet another object of the invention is to provide delayed transaction buffers and counters as improvements to PCI target devices utilizing delayed transactions.
These and other objects will become apparent in the description that follows.
As used herein, xe2x80x9cVLSIxe2x80x9d stands for very large integration integrated circuits. VLSI designation is made for convenience only with respect to integrated circuits of the invention and can include ultra large scale integration (xe2x80x9cULSIxe2x80x9d) devices.
In one aspect, the invention provides an efficient implementation of a low cost PCI delayed transaction time out counter. Such a delayed transaction counter of the invention includes delayed transaction buffers of a slave coupled to a master on a PCI bus. In one aspect, the counter includes a free running n-bit counter and a plurality m-bit time out counters coupled to the free running n-bit counter. Each time out counter couples to an associated delayed transaction buffer of the slave; and each time out counter generates a flush signal which deletes delayed transaction information stored within the associated buffer after a time out period. Each time out counter is thereafter reset to zero after receipt of a delayed transaction by the associated delayed transaction buffer.
In another aspect, there includes means, such as an AND gate, for incrementing each time out counter by one.
In one aspect, the counter includes means, such as an AND gate, for restarting each time out counter after a PCI delayed transaction.
In other aspects, the n-bit counter is implemented as an 8-bit counter or a 6-bit counter; and the m-bit counter is implemented as an 8-bit counter or a 10-bit counter.
In yet another aspect, the invention provides improvements to a slave device of the type which stores delayed transactions from a master on a PCI bus. The improvement includes a free running n-bit counter and a plurality m-bit time out counters coupled to the free running n-bit counter. Each time out counter couples to an associated delayed transaction buffer of the slave, and each time out counter generates a flush signal which deletes delayed transaction information stored within the associated buffer after a time out period. Each time out counter is reset to zero after receipt of a delayed transaction by the associated delayed transaction buffer.
In another aspect, the invention provides a PCI VLSI device operating as a slave to a master on a PCI bus. A plurality of delayed transaction buffers store delayed transaction information data, the data being used by the slave in a subsequent retry by the master to complete a transaction on the bus. A counter section times a time period for which the data is stored within each of the buffers. Each of the buffers is flushed when the time period exceeds a preselected time out period.
In one aspect, the counter section of this aspect includes a free running n-bit counter and a plurality m-bit time out counters coupled to the free running n-bit counter. Each time out counter couples to an associated delayed transaction buffer of the slave, and each time out counter generates a flush signal used by the device to delete delayed transaction information stored within the associated buffer after the time out period.
In other aspects, the invention includes means for resetting each time out counter to zero after receipt of a delayed transaction by the associated delayed transaction buffer, and/or means for incrementing each time out counter by one. A PCI VLSI device of the invention can include a 16-bit counter for each delayed transaction buffer such that delayed transactions are flushed from the buffer within 215 clock cycles.
In yet another aspect, the invention includes a method for clearing a delayed transaction buffer associated with master-to-slave transactions on a PCI bus, including the steps of: counting time via clock cycles following receipt of a delayed transaction within the buffer; and flushing the buffer after the time exceeds a preselected limit.
The invention is next described further in connection with preferred embodiments, and it will become apparent that various additions, subtractions, and modifications can be made by those skilled in the art without departing from the scope of the invention.